ARM7 Ports

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Contents

General

ARM7 is 32-bit RISC von Neumann processor. As user processes runs in System mode, 16 registers accessible by process:

  • 1 register is Status Register (CPSR);
  • 1 register is R15, Program Counter (PC);
  • 1 register is R14, Link Register (LR);
  • 1 register is R13, Stack Pointer (SP);
  • 13 general purpose registers R0-R12 (GPR).

Therefore, context in the processor consists of:

   13 (GPR) + 1 (PC) + 1 (LR) + 1 (CPSR) = 16 registers or 16*4 = 64 bytes.

This means that each user's process must have stack greater at least context size (64 bytes) + call depth multiplied by 4. SP register contents stored in kernel's process table.

The Port uses one common stack for data and return addresses.

Program Control Flow Transfer

Both methods - direct and software interrupt - are supported in the ARM7 port, except ADuC port, where only direct method is supported because of absence of interrupt controller.

In case of direct program control flow transfer there are no any peculiarities.

In case of software interrupt program control flow transfer a situation is the following: if interrupt controller has dedicated software interrupt, this interrupt is used (as in LPC2xxx port). If there is no special software interrupt, one of unused hardware interrupts has been used. Any scmRTOS release has default Software Context Switch interrupt assignment. The user can leave this default assignment or change the assignment by analogy with defaults according to his project requirements. This assignment is defined in project-dependent part of the RTOS - scmRTOS_TARGET_CFG.h header file.

Interrupts

The using of interrupts with scmRTOS does not make any special demands. The user should keep in mind those things:

  • only IRQ exception can use OS services, not FIQ;
  • IRQ exception handler implemented in scmRTOS_Target.s79;
  • interrupt service routine (ISR) functions must be qualified with OS_INTERRUPT macro;
  • TISRW object must be declared at the beginning of ISR which uses OS services. This object involves constructor and destructor that play very important role in the RTOS rescheduling mechanism and integrity.
  • in case of direct program control flow transfer ISR function which is not uses OS services must be implemented in same way as ISR function which is uses OS services.
  • in case of software interrupt program control flow transfer, ISR function which is not uses OS services can be implemented in same way as ISR function which is uses OS services, but it leads to some overhead in TISRW object constructor and destructor. If overhead is undesirable, ISR function must still be qualified with OS_INTERRUPT macro, but instead of declaring TISRW object at the begining of ISR it must contain IRQ_DONE() macro at the end of function.

main() function stack (CSTACK) occupies the same space as IRQ stack (because interrupts are disabled before RTOS starts). Therefore, this stack depth is defined to be zero-sized in linker script. IRQ stack depth defined in linker script by directive:

 -DIRQ_STACK_SIZE=N

where N - size of the stack.

System Timer

scmRTOS v4 allows user to choose any available hardware timer, fully setup the timer and setup interrupt vector of the timer. As Software Context Switch interrupt assignment, any scmRTOS release has default timer assignment. The user can leave this default assignment or change the assignment by analogy with defaults according to his project requirements. All project-dependent definitions of System Timer hardware implementation (setting, interrupt vector, etc.) resided in project-dependent part of the RTOS - scmRTOS_TARGET_CFG.h header file.

Summary

See Release info for more details about port features and using examples:

And, as usual, see Documentation for more details about RTOS contents, structure, functionality and features.

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