Cortex™-M3 is new ARM 32-bit RISC core with Harvard bus architecture.
Unlike previous ARM CPU's, Cortex™-M3 standartizes complete processor architecture, including interrupt system, SysTick timer and memory map. This allows to write one scmRTOS port for whole Cortex™-M3 family.
As user processes runs in Thread mode, 16 registers accessible by process:
- 1 register is Status Register (CPSR);
- 1 register is Program Counter (PC);
- 1 register is Link Register (LR);
- 1 register is Stack Pointer (SP);
- 13 general purpose registers R0-R12 (GPR).
Therefore, Cortex™-M3 processor context consists of:
13 (GPR) + 1 (PC) + 1 (LR) + 1 (CPSR) = 16 registers or 16*4 = 64 bytes.
It means that each user's process must have stack greater at least context size (64 bytes) + call depth multiplied by 4. SP register contents stored in kernel's process table.
The Port uses one common stack for data and return addresses.
Program Control Flow Transfer
Only one method - software interrupt - is supported in the port. This is because Cortex™-M3 processor has native Software Interrupt that is very suitable for implementation of context switch.
Main stack. Main program (tasks) utilize
The using of interrupts with scmRTOS does not make any special demands. The user should keep in mind those things:
- interrupt service routine (ISR) functions must be qualified with
TISRWobject must be declared at the beginning of ISR which uses OS services. This object involves constructor and destructor that play very important role in the RTOS rescheduling mechanism and integrity.
System tick timer is used as the OS SystemTimer.
All settings of the System Timer are done by the OS except timer clock frequency. Timer clock frequency and timer's interrupt rate must be set up by the user (with macros
scmRTOS_TARGET_CFG.h header file).
Currently there are two scmRTOS port implementations for Cortex™-M3:
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